1. Field of Invention
This invention relates to a semiconductor device and a method of producing the same, and more particularly to a semiconductor device which operates under a low power supply voltage and a method of producing the same.
2. Description of the Related Art
Semiconductor integrated circuits have exhibited remarkable progress together with the development of fine working technique, and now, a very large scale circuit can be formed on a single semiconductor chip. One of problems involved in this is an increase in power dissipation of a semiconductor chip arising from an increase of the circuit scale. Particularly in apparatus with which importance is attached to the portability, since a battery is used as a power supply, the increase of the power dissipation may possibly create a fatal problem.
In a so-called CMOS integrated circuit, since the power dissipation when it operates increases substantially in proportion to the square of the power supply voltage, a concrete solution to the increase of the power dissipation is to make the power supply voltage lower. Further, to make the power supply voltage lower is an essential demand involved in reduction in physical dimension of a MIS field effect transistor. On the other hand, however, to make the power supply voltage lower gives rise to another problem of a drop in operation speed.
In particular, although, from the principle of operation of a MIS field effect transistor, the amount of the driving current increases in proportion to the amount of charge produced in a channel region of the transistor, the amount of charge also increases in proportion to the "input gate voltage--threshold voltage". In a standard CMOS circuit, the maximum input voltage is equal to the power supply voltage. Accordingly, as the power supply voltage is made lower until it approaches the threshold voltage, the driving current of the MIS field effect transistor decreases, and consequently, the operation speed decreases rapidly.
In order to eliminate this problem, as the power supply voltage decreases, the threshold voltage of the MIS field effect transistor must be made lower simultaneously.
However, the sub threshold current of the MIS field effect transistor exponentially relies upon the gate voltage, and in order to suppress the off current of the transistor to a level at which no problem occurs, the threshold voltage of the MIS field effect transistor cannot be set very low. Particularly, the limit value to the threshold voltage is approximately 0.4 volt in absolute value.
In order to solve those contradictory problems, several solutions have been proposed.
One of the solutions is a method wherein a power supply is cut off as disclosed in Matsutani et al., "1 V, 10 MHz High-Speed Digital Circuit Technology with Multi-Threshold CMOS", TECHNICAL REPORT OF IEICE, ICD 93-107, pp.23-27. A logic circuit is formed from transistors having a low threshold voltage, and an integrated circuit operates at a high speed. Mean-while, when the integrated circuit is not in an operating condition, the power supply is disconnected by means of a switch to prevent an unnecessary current from flowing. Where this construction is employed, the threshold voltage of the transistors can be set independently of the sub threshold current.
Another one of the solutions is a method wherein a deep substrate bias is applied to transistors to raise the threshold voltage of the transistors. The leak currents of the transistors can be reduced thereby. This method is disclosed, for example, in Japanese Patent Laid-Open No. Hei 3-82151 and Japanese Patent Laid-Open No. Hei 5-108194.
The methods described above, however, have various problems.
With the former method, a switch for disconnecting the power supply is required. While, in an ordinary integrated circuit, it cannot be avoided to use a transistor for the switch, in order to realize an insertion loss which makes no problem in practical use, the on-resistance of the transistor must be made very low, and to this end, an overhead of a large area is required. The former method also has another problem in that data stored in latch circuits or like elements are all lost by disconnection of the power supply.
In order to avoid this problem, in the former method, the latch circuits must be connected to the power supply by different wirings. This results in increase in complication in designing.
In the latter method, power consumption in a substrate bias generation circuit itself is a problem. In particular, the latter method presents a contradiction in that, when the integrated circuit is in a standby state in which the power consumption should be suppressed low, the substrate bias generation circuit must operate causing consumption of the power.